Poduel, Bikash, Prasanna Kansakar, Sujit R. Chhetri, and Shashidhar Ram Joshi. 2015. “Design and Implementation of Synthesizable 32-Bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL”. Nepal Journal of Science and Technology 15 (1):81-88. https://doi.org/10.3126/njst.v15i1.12021.