Poduel, B. et al. 2015. Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL. Nepal Journal of Science and Technology. 15, 1 (Feb. 2015), 81–88. DOI:https://doi.org/10.3126/njst.v15i1.12021.